1. Field of the Invention
The present invention relates to suppression of large currents in a transistor circuit which uses an MOS transistor.
2. Description of Related Art
In circuits which operate using a battery as a power source, reduction of voltage in the power source has been conventionally demanded, and circuits which operate using a battery power source of 3V or 1.5V are becoming common. On the other hand, there are circuits in which high voltage is required, and a charge pump circuit (a booster circuit) and a level shift circuit are therefore often used to generate high voltage by means of a battery power source.
Such a booster circuit is described in, for example, Japanese Patent Laid-Open Publication No. Hei 7-298607.
However, such conventional booster circuits suffer from a problem in that, when a short circuit occurs at the output side, a large current will flow through the circuit. The inventors of the present application studied this problem and recognized that such large currents, which the refer to as a “high current” flows from a power source via a parasitic diode formed in a transistor which is used in a booster circuit.
Voltage boosting using a CMOS which is shown in FIG. 1 can provide an example. Referring to FIG. 1, a power source voltage VDD on the input side is connected with a source of an NMOS 10. A drain of the NMOS 10 is connected with one end of a shifting capacitor 12, to which a pulse voltage is supplied from the other end. The drain of the NMOS 10 is also connected to a drain of a PMOS 14, and a source of the PMOS 14 is connected with a voltage holding capacitor 16 and also with an output terminal 18.
An identical clock signal is supplied to gates of the NMOS 10 and the PMOS 14.
In the circuit thus configured, when a clock signal is high (H), the NMOS 10 turns on and the PMOS 14 turns off, and voltage VDD is held in the shifting capacitor 12. On the other hand, when a clock signal is low (L), the NMOS 10 turns off and the PMOS 14 turns on. In this state, by applying a pulse signal for voltage shifting to shift the voltage of the shifting capacitor 12 by an amount of voltage VDD, for example, voltage of 2VDD is held in the holding capacitor 16 and is output.
FIG. 2 shows a structure of an NMOS. As shown, a pair of N regions are formed within a P well to provide a source S and a drain D, and a gate electrode G is formed via an insulating film in the channel region between the source S and the drain D. Further, a P++ region is also formed within the P well to provide a back gate BG. With this structure, a parasitic diode due to P-N junction is formed from the back gate BG toward the source S and the drain D.
FIG. 3 shows a structure of a PMOS. As shown, a pair of P regions are formed within an N well to provide a source S and a drain D, and a gate electrode G is formed via a gate insulating film in the channel region between the source S and the drain D. Further, an N++ region is also formed within the N well to provide a back gate BG. With this structure, a parasitic diode due to P-N junction is formed from the source S and the drain D toward the back gate BG.
Further, FIG. 4 shows an NMOS having a triple-well structure in which the above-described P well is contained within an N well. In this structure, a parasitic diode from the back gate BG to the N well is further added.
FIG. 5 shows the route of current when the NMOS having a triple-well structure of FIG. 4 and the PMOS shown in FIG. 3 are applied to the booster circuit of FIG. 1 and short circuit is caused in the output.
In this booster circuit, with regard to both MOS's, the source S and the back gate BG are short-circuited in their normal use, and the output terminal 18 is connected with the N well so as to provide a high potential.
In a booster circuit, the output side is normally at a high voltage, and in such a case, a parasitic diode would not create a problem. When the output is short-circuited to ground, however, short-circuit current flows from the power source via the parasitic diode. Specifically, an example short-circuit route would be power source VDD→source S of NMOS→back gate BG→N well→output terminal 18, which is defined as a route (i). Another short-circuit route would be power source VDD→source S of NMOS→back gate BG of NMOS→drain of NMOS→drain of PMOS→back gate BG of PMOS→source of PMOS→output terminal 18, which is defined as a route (ii).
In particular, with regard to the route (i) which is a short-circuit route with only one diode, high current flows and this significantly affects the circuit. The route (ii), on the other hand, passes through two diodes and therefore affects less significantly than the route (i). However, some measures should also be taken to account for the route (ii).